Series, Parallel, Delta & Wye Resistive Reductions
Resistive reduction removes internal nodes while preserving terminal behavior. Series and parallel rules are local; delta-wye conversion handles three-terminal resistor networks that contain neither pattern.
An equivalent resistor network must preserve the voltage-current relation seen at its exposed terminals. Reduction is therefore an elimination operation: internal node voltages and branch currents disappear, but no external experiment can distinguish the reduced network from the original over the modeled range.
Series and parallel tests #
Two resistors are in series only when their shared node has no third connection, forcing the same current through both:
They are in parallel only when both ends connect to the same two nodes, forcing the same voltage across both:
Visual alignment on a schematic proves neither condition. Node identity does.
Delta to wye #
For a delta with edge resistances , , and , let . The equivalent wye arms are
For the reverse conversion, with wye arms and :
The formulas preserve resistance between each pair of external terminals with the third terminal left open.
Reduction strategy #
- label nodes before looking for patterns;
- reduce unambiguous series/parallel groups;
- use delta-wye only when it exposes a new reduction;
- stop when reduction would hide a requested internal current or voltage;
- use nodal or mesh analysis when algebraic reduction grows rather than shrinks.
The open-third-terminal check is necessary but not sufficient by itself; repeat it for all three terminal pairs. Equality of those three pairwise resistances establishes the three-terminal equivalence for a passive resistive network.