Computer Architecture

A microprocessor system is a set of state-owning components coordinated by bus transactions: the CPU issues instruction and data accesses, memory and peripherals respond to decoded addresses, and interrupt or DMA logic changes who needs service or who owns the bus.

Memory channels are independent controller-to-DRAM interfaces: populating more channels raises aggregate transfer capacity by letting the controller serve interleaved cache lines concurrently, but it does not halve DRAM latency or guarantee a proportional application speedup.

Assembly source is not an executable: the assembler encodes sections and unresolved references into an object file, the linker lays out and relocates those objects, and debug metadata lets tools reconnect machine addresses to symbols and source.

A microcontroller integrates a CPU, memories, clocks, reset logic, pins, and stateful peripherals, but firmware still has to satisfy the contract at every boundary: power and clock validity, register semantics, event ownership, pin routing, and safe sequencing.

The MCS-51 contract combines an accumulator-centered 8-bit CPU with distinct code and data spaces, banked and bit-addressable internal RAM, SFR-controlled peripherals, and instruction-dependent address-space selection. Modern compatible cores preserve that model while changing timing and peripherals.

MCS-51 instructions are best understood as routes among the accumulator, register banks, internal data, SFRs, bit space, code tables, and external data—not as a flat mnemonic list. Each addressing form determines both where an operand lives and which side effects are possible.

Classic 8-bit AVR couples thirty-two working registers to a single-cycle-oriented ALU, while separate program, data, I/O, EEPROM, and device-dependent extended address state shape every load, call, interrupt, and boot operation.

Clock, reset, power monitoring, sleep, and watchdog logic form one lifecycle system: they decide when state may advance, which state survives, how startup becomes valid, and whether a stalled program can recover into a known condition.

A microcontroller pin is the meeting point of a pad, input buffer, output driver, pull device, digital latch, analog switch, and peripheral router. Correct GPIO work separates requested logic state from driver mode, route ownership, and measured pad voltage.

An interrupt is a negotiated ownership transfer: hardware records an event, mask and priority logic decide eligibility, the core saves architectural return state, software services and acknowledges the source, and an interrupt return restores the prior execution contract.

A timer is a clocked state machine with selectable clock, counter width, terminal rule, capture and compare events, output actions, buffering, and interrupts. PWM is one consequence of those transitions—not a separate analog voltage source.

UART, SPI, and I²C move framed state over pins under different clock, ownership, addressing, and electrical contracts. Reliable firmware follows each transfer from clock generation and pin routing through shift state, flags, buffering, errors, and acknowledgement.

An MCU ADC is a switched acquisition system tied to a reference, pin multiplexer, clock, sample capacitor, converter, result register, and event logic. Correct codes require both analog settling and a race-free firmware lifecycle; a comparator provides a different one-bit threshold path.

Flash, EEPROM, fuse/configuration state, lock bits, boot sections, and debug/programming ports have different write granularities and protection rules. Programming is a power-sensitive state transition with explicit authority, not an ordinary memory store.

The 8086 exposes sixteen-bit data, pointer, segment, instruction, and flag registers while its original implementation splits execution from bus access and overlaps both through a six-byte prefetch queue. The register contract survived far longer than that implementation.

Real-mode x86 forms a twenty-bit address from a sixteen-bit segment and offset, so many logical addresses alias the same byte. The original 8086 then maps bytes onto two eight-bit memory banks selected by A0 and BHE#, making alignment visible as bus cycles.

8086 instructions combine opcode-specific fields with an optional ModR/M byte, displacement, and immediate data. Decoding works by separating register selection, effective-offset formation, segment selection, and little-endian payload bytes.

The 8086 instruction set is easier to reason about as state transformations: data movement selects locations, arithmetic and logic define flag evidence, string operations advance implicit indexes, and port I/O crosses into a separate address space.

8086 control transfers either replace IP within a code segment or replace CS:IP across segments. Calls and interrupts make that transfer reversible by building precise word frames on SS:SP; RET, RETF, and IRET consume different frames.

Booting is a chain of explicit contracts: reset selects firmware, firmware selects a loader, the loader constructs a kernel image and handoff record, and only then does the kernel take ownership of the machine.

Real mode, protected mode, and IA-32e mode are coordinated contracts among control registers, descriptors, paging, stacks, and event delivery—not interchangeable names for operand width.

How Intel 64 turns a linear address into a physical address, enforces page permissions, caches translations, and makes page-table changes visible across CPUs.

How Intel 64 combines coherent caches, store buffers, PAT and MTRR memory types, atomic operations, fences, and cache-management instructions into the software-visible memory contract.