MCS-51 Addressing & Instruction Set

The MCS-51 instruction set is compact because operand location is encoded through several specialized forms. Learning it as “256 opcodes” obscures the real structure: the instruction selects an address space, an operand route, and a set of architectural effects.

Addressing forms #

The mnemonic MOV is not one universal move. Its operand forms decide which memory exists on each side and what encoding is legal. MOVC explicitly reads code space; MOVX explicitly accesses external data space.

Data movement and exchange #

Moves connect the accumulator, registers, direct bytes, indirect bytes, SFRs, external data, and code tables. Stack instructions operate on internal data through SP. XCH and nibble exchange support compact transformations but also create implicit accumulator dependencies.

For table lookup, MOVC A,@A+DPTR uses DPTR as a base and A as an index, then overwrites A with the fetched byte. A routine that still needs the index must preserve it. This is a general reading rule: list every implicit input and output, not only operands printed by the assembler.

Arithmetic and flags #

Addition and subtraction update carry-related flags; ADDC consumes carry and supports multi-byte arithmetic. SUBB subtracts both the operand and the input borrow represented by carry, so firmware must establish the initial carry state deliberately.

MUL AB produces a 16-bit result split across B:A; DIV AB returns quotient and remainder. Decimal adjustment is meaningful only after the intended BCD addition sequence. Increment/decrement instructions do not all update carry in the way a programmer familiar with another ISA may expect.

Boolean processor #

The carry flag acts as a one-bit accumulator. Instructions can move between carry and an addressed bit, combine carry with a bit or its complement, set/clear/complement bits, and branch on bit state while optionally clearing it.

This is powerful for control firmware because a pin, flag, or software bit can be manipulated without a byte-wide mask sequence. It is also concurrency-sensitive: a peripheral flag may change asynchronously, and a read-modify-write operation on a port or SFR may observe the latch rather than the external signal.

Control flow and reach #

• short conditional branches use signed relative offsets;
• SJMP is compact but local;
• AJMP/ACALL encode a destination within a page-related reach;
• LJMP/LCALL carry a full 16-bit code address;
• RET restores a normal call return;
• RETI also completes the interrupt-controller protocol expected by the architecture/device.

Assembler and linker placement matter because a source-level call can require a different encoding when code moves. Hand-written absolute assumptions become fragile as soon as modules are linked or boot regions are introduced.

A worked multi-byte addition #

To add two 16-bit little-endian values:

1. clear carry;
2. load the low byte of the first operand into A;
3. add the low byte of the second operand and store the result;
4. load the high byte of the first operand;
5. use ADDC with the second high byte;
6. store the high result; carry now records unsigned overflow beyond 16 bits.

The algorithm works because the low-byte instruction produces the exact carry state consumed by the high-byte instruction. An interrupt that modifies A, carry, DPTR, or selected bank without preserving it breaks the chain.

Timing belongs to the implementation #

Instruction semantics come from the architecture; cycle counts come from a particular core and memory system. The original 8051 organized work around twelve oscillator periods per machine cycle. Modern compatible cores can execute most instructions in one or two system clocks. Delay loops must therefore be derived from the exact device clock and instruction timing—or replaced by a timer whose behavior is itself specified.