Operational Amplifiers & Precision Building Blocks

An operational amplifier produces $v_o=A_{OL}(v_+-v_-)$, with very large but finite, frequency-dependent open-loop gain. Feedback drives the differential input small enough that a simpler external network determines closed-loop behavior. “The inputs are equal” and “no input current flows” are therefore approximations to verify, not physical laws.

Canonical closed-loop functions #

For an inverting amplifier,

$$\frac{v_o}{v_i}=-\frac{R_f}{R_{in}},$$

assuming loop gain is large and the non-inverting input reference is valid. The inverting node is a virtual reference, not a short to ground: its voltage stays near the reference only while the amplifier remains in its linear envelope.

For a non-inverting amplifier,

$$\frac{v_o}{v_i}=1+\frac{R_f}{R_g}.$$

KCL at the summing node generalizes to weighted summing, transimpedance conversion, active integration, differentiation, and filtering.

flowchart TB
  VIN["input network"] --> SUM["summing node"]
  REF["reference / bias"] --> OP["finite op amp<br/>Aol, GBW, SR, limits"]
  SUM --> OP
  OP --> OUT["output + load"]
  OUT --> FB["feedback network"]
  FB --> SUM

The real error budget #

Resistor choice trades output loading against current-noise and parasitic-capacitance sensitivity. Very small values waste current and heat the output stage; very large values amplify bias-current error and noise and create low-frequency poles with stray capacitance.

Small-signal and large-signal limits differ #

For a dominant-pole voltage-feedback op amp, closed-loop bandwidth is roughly GBW divided by noise gain. But a sine wave of peak amplitude $V_p$ and frequency $f$ demands

$$SR_{required}=2\pi fV_p.$$

An amplifier can meet its small-signal bandwidth yet slew-limit a large output. Settling time also includes linear ringing plus nonlinear overdrive recovery; neither follows from GBW alone.

Supply and reference discipline #

Single-supply circuits require a valid signal reference, often a buffered midrail or ground-referenced architecture designed for the needed common-mode range. “Rail-to-rail” may describe input, output, or both, under specified load and temperature; it never means zero distance to both rails under every condition.

Decoupling belongs at the device pins with a tight return path. Capacitive load can erode phase margin; an isolation resistor or in-loop compensation may be required. The output must be checked for current, power dissipation, short-circuit behavior, and stability with the real cable, ADC input, or capacitive sensor.