PLC Execution: Tasks, Scan Cycles, I/O Images & Remote I/O

A PLC turns changing physical signals into repeatable control decisions by scheduling tasks against coherent I/O data, publishing outputs at defined boundaries, and detecting overruns and stale remote data. The classic input–logic–output scan is a useful model, but modern multitasking and asynchronous networks make the exact update contract essential.

A PLC runtime is a temporal contract between physical I/O, application logic, and outputs. The important question is not merely “does this rung evaluate true?” but which input version did it see, when can another task change shared state, and when does the resulting output reach the field? The classic scan gives one good answer; modern runtimes provide several others.

The canonical scan #

In the simplest cyclic executive, the controller repeats:

  1. copy physical inputs into an input process image;
  2. execute application logic against that stable image;
  3. copy the output process image to output modules;
  4. perform diagnostics and communications, then begin again.
PLC scan and I/O timeline A timeline shows remote input transport, input image capture, two scheduled tasks, output image publication, and remote output transport. A field change just after capture waits until the next task release. One decision spans several clocks t₀input snapshottask releaseoutput publishfield acts Field input module filter + network change just missed snapshot Input image coherent version N Controller Task A Task B Output image assignments accumulate Field output module + network waits for version N+1 Value + source time + quality make age observable.
The process image makes one execution interval coherent; remote transport and task scheduling still add age, jitter, and output delay.

This snapshot prevents a long program from seeing one contact as false near the top and true near the bottom merely because the field changed mid-scan. The cost is latency. A change just after the input copy waits almost one cycle to be sampled, then the program executes, then the output waits for publication and module transport.

For a cyclic task with period TT, an approximate end-to-end delay is

D≈Dinput transport+ϕsample+Dqueue+Ctask+Doutput publication+Doutput transport,D \approx D_{\text{input transport}} + \phi_{\text{sample}} + D_{\text{queue}} + C_{\text{task}} + D_{\text{output publication}} + D_{\text{output transport}},

where sample phase ϕsample\phi_{\text{sample}} lies between nearly zero and nearly TT. Quoting only the average scan time hides the worst phase and every network/module delay around it.

Process image versus physical I/O #

Access Strength Risk
Process-image read coherent task view, easy simulation value has acquisition age
Direct/immediate read sees a later physical value breaks snapshot reasoning; transport may still be cached
Process-image write several calculations resolve before one publication field does not change at the assignment statement
Immediate output low-latency exceptional action timing and ownership become path-specific

An address such as %I0.0 or a symbolic input may name a memory image, not an electrical terminal sampled at that instruction. Likewise, assigning an output variable usually changes controller memory first. The hardware module updates at the runtime's defined boundary or fieldbus cycle.

Tasks, priorities, and watchdogs #

IEC 61131-3's software model allows tasks to trigger programs or function blocks periodically or on an event. Commercial controllers also commonly provide continuous/background, periodic, and event tasks. A higher-priority task may preempt a lower-priority task, so its response improves at the expense of jitter and completion time below it.

For each task, measure or bound:

  • release period and phase;
  • worst observed and justified worst-case execution time;
  • preemption and blocking from higher priorities or shared resources;
  • deadline and tolerated jitter;
  • watchdog action after an overrun.

CPU utilization below 100% does not prove schedulability. A 2 ms event task can repeatedly preempt a 10 ms control task at exactly the wrong phase. Nor does a watchdog “fix” an overrun: it detects that the temporal contract has already failed and transfers control to a configured fault policy.

Shared data and execution order #

Within one task, program order often supplies determinism: later logic sees values written earlier in the same invocation. Across tasks, a shared variable can be read while another task is updating a related group of fields. Use a single owner for each output and state machine; exchange coherent structures at explicit boundaries; and include sequence counters or timestamps when readers must detect a new publication.

Double buffering is a useful pattern:

  1. a producer writes an inactive buffer completely;
  2. it increments a sequence and atomically publishes the buffer identity;
  3. the consumer snapshots the identity and reads only that buffer;
  4. a changed sequence during the read invalidates the snapshot.

The exact atomic operations remain runtime-specific, but the invariant is portable: the consumer never interprets a half-old, half-new control object.

Remote I/O is a sampled networked system #

Remote I/O adds producer cycles, network scheduling, gateway queues, module filtering, and loss/recovery behavior. The controller's input image may be internally coherent yet already too old for the process. Preserve at least:

  • raw value and engineering value;
  • source or acquisition timestamp when available;
  • quality/status and substitution state;
  • expected update period and staleness limit;
  • module and network diagnostic state.

A Boolean without age or quality cannot distinguish “false now” from “last false value retained after the remote rack disappeared.” For a permissive or trip input, that difference is part of the control requirement.

Startup, restart, and retained state #

Cold start, warm restart, program download, transition to RUN, and task fault are different events. Define which variables initialize, which retain their value, how output modules behave before the first valid publication, and whether a sequence may resume automatically. Retaining a motor's Running state across power loss is not equivalent to proving that the motor is running; physical feedback must re-establish reality.

Timing trace for one input #

Suppose a 10 ms periodic task executes for at most 2 ms, an input module publishes every 4 ms, and the output fieldbus publishes every 4 ms. Ignoring phase alignment, a physical change can wait almost 4 ms for input transport, almost 10 ms for task release, 2 ms for execution, and almost 4 ms for output transport: nearly 20 ms. The average may be about half that. Both numbers are more useful than “the scan is 2 ms,” because the 2 ms covers only computation.

Commissioning checks #

Measure input acquisition-to-image delay, task release jitter, execution high-water mark, output-image-to-terminal delay, and behavior under communication loss. Force a controlled task overrun and verify the watchdog path. Power-cycle a remote rack and the controller separately. Confirm that stale quality reaches both control logic and HMI. Finally, prove that every physical output has one software owner or an explicit arbitration block; multiple writers make scan order an undocumented control policy.

Sources

  1. docsIEC 61131-1:2003 — Programmable Controllers, General Information
  2. docsOPC 30000 — PLC Model Based on IEC 61131-3
  3. docsRockwell Automation — Logix Tasks
  4. docsBeckhoff — TwinCAT Process Images and Task Mapping

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