Digital Controller Synthesis, Polynomial Design & Deadbeat Control

Digital controllers can be obtained by discretizing a continuous design, designing directly in the z-plane, solving a polynomial model-matching equation, or using discrete state space. Each route must satisfy causality, internal stability, sampling-zero, delay, robustness, and actuator constraints; deadbeat response is a fragile finite-sample ideal, not free speed.

A digital design starts with a sampled plant and an explicit delay convention. The controller must be a causal recurrence that can execute before its deadline. A rational solution that cancels a forbidden zero, requires future samples, or exceeds actuator authority is not a controller even if its nominal transfer function matches the requested response.

Discrete pole placement and deadbeat responseThe left panel shows a unit circle with an open-loop pole a moved to a chosen closed-loop lambda and then to zero for deadbeat control. The right panel compares geometric sample response with finite-settling deadbeat response. aλ0K=(a−λ)/b · deadbeat chooses λ=0final valuegeometric λᵏdeadbeat finite settlingfewer samples usually demand more control effort

Moving the pole toward zero shortens the sample-count transient but usually increases command effort and sensitivity. Deadbeat places it at zero only in the ideal model.

Four design routes #

Emulation #

Design C(s)C(s) with continuous methods, then discretize it by Tustin, matched pole-zero, ZOH-equivalent state update, or another justified method. Emulation is attractive when TsT_s is fast relative to crossover and a trusted continuous design exists. Always close the loop around the discrete plant and include hold/delay; discretizing the controller does not preserve every continuous closed-loop property.

Direct z-plane design #

Use root locus, Bode response on z=ejΩz=e^{j\Omega}, Nyquist, or direct pole placement on the pulse model. Stability lies inside the unit circle. Desired continuous pole sds_d maps to zd=esdTsz_d=e^{s_dT_s}, but performance must still be checked in seconds and between samples.

Polynomial design #

Let plant and controller be

G(z)=B(z)A(z),D(z)=R(z)S(z).G(z)=\frac{B(z)}{A(z)},\qquad D(z)=\frac{R(z)}{S(z)}.

For unity negative feedback, the characteristic polynomial is

A(z)S(z)+B(z)R(z).A(z)S(z)+B(z)R(z).

Choose desired Ac(z)A_c(z) and solve the Diophantine equation

A(z)S(z)+B(z)R(z)=Ac(z).A(z)S(z)+B(z)R(z)=A_c(z).

Controller degrees must provide enough unknown coefficients for a solution. Common factors of AA and BB, delays, and causality constraints affect solvability. Reference prefilter T(z)T(z) can shape nominal tracking without changing the feedback characteristic polynomial.

State-space design #

For

x[k+1]=Adx[k]+Bdu[k],x[k+1]=A_dx[k]+B_du[k],

choose u[k]=−Kx[k]+Nr[k]u[k]=-Kx[k]+Nr[k] by discrete pole placement or LQR, provided the unstable modes are controllable. Add an observer or estimator when state is not measured. This route represents delays and multivariable structure more directly than scalar polynomial algebra.

Worked first-order pole placement #

Consider

y[k+1]=ay[k]+bu[k],b≠0.y[k+1]=ay[k]+bu[k],\qquad b\ne0.

With

u[k]=−Ky[k]+Nr[k],u[k]=-K y[k]+N r[k],

closed-loop dynamics are

y[k+1]=(a−bK)y[k]+bNr[k].y[k+1]=(a-bK)y[k]+bNr[k].

Place the pole at λ\lambda:

K=a−λb.K=\frac{a-\lambda}{b}.

For unit steady tracking of constant rr,

N=1−λb.N=\frac{1-\lambda}{b}.

The response is

y[k]=r+λk(y[0]−r).y[k]=r+\lambda^k(y[0]-r).

Choosing λ=0\lambda=0 gives ideal one-step decay of the state error. But the initial command becomes u[0]=−(a/b)y[0]+r/bu[0]=-(a/b)y[0]+r/b, which can be large when bb is small. Saturation destroys the one-step prediction and can create a much longer nonlinear transient.

Deadbeat control #

A deadbeat closed loop reaches its final sampled value in a finite number of samples. For a finite-dimensional causal LTI sequence model, this means the relevant closed-loop transfer has a finite impulse response; in a minimal state realization, closed-loop poles are at z=0z=0.

Deadbeat design is constrained by:

  • plant and computation delays, which set a minimum response horizon;
  • unstable or nonminimum-phase zeros, which cannot be cancelled internally;
  • relative degree and controller properness;
  • actuator magnitude/rate;
  • model uncertainty and quantization;
  • intersample behavior.

Longer finite-settling designs can distribute command effort over more samples. An “aperiodic” or monotone discrete response may be preferable to the shortest algebraic horizon.

Desired closed-loop transfer functions #

Choosing Y/R=M(z)Y/R=M(z) and solving

D(z)G(z)1+D(z)G(z)=M(z)\frac{D(z)G(z)}{1+D(z)G(z)}=M(z)

formally gives

D(z)=M(z)G(z)[1−M(z)].D(z)=\frac{M(z)}{G(z)[1-M(z)]}.

This formula is a feasibility test, not an automatic design. Check whether it:

  • is causal and proper under the chosen z−1z^{-1} convention;
  • has stable controller poles;
  • avoids cancellation of unstable plant poles or zeros;
  • yields internal stability for every exogenous-to-internal map;
  • tolerates plant and delay uncertainty;
  • respects control and sample-rate constraints.

If any primary condition fails, reject the desired map rather than adding a hidden workaround.

Unstable and nonminimum-phase plants #

An unstable plant requires feedback that stabilizes its modes; those modes cannot disappear through nominal cancellation. A zero outside the unit circle imposes inverse-response and speed limits. Model matching must factor stable/unstable parts and preserve the forbidden zero structure in the achievable closed-loop response.

Sampling itself can create nonminimum-phase zeros. Revisit TsT_s and the physical interface before blaming the controller architecture.

Integral action and digital PID #

A pole at z=1z=1 embeds a constant internal model and can remove constant steady error in a stable loop. Digital PID may be designed directly as a recurrence or obtained from a continuous form, but coefficient formulas depend on integration/derivative approximations and sample period. Preserve anti-windup, derivative filtering, setpoint weighting, and update order from the PID implementation.

Synthesis acceptance test #

  1. Verify sampled plant, delays, zeros, and sample-time units.
  2. Prove stabilizability/internal stability before model matching.
  3. Check controller causality and implementation order.
  4. Compute reference, disturbance, noise, and control-effort maps.
  5. Test pole/margin sensitivity to coefficients, delay, and plant uncertainty.
  6. Simulate saturation, rate limits, quantization, missed samples, and intersample peaks.
  7. Run the actual numeric realization and target timing.

The most aggressive sample-count response is rarely the most robust physical response.

Sources

  1. bookDigital Control Systems: Lecture Notespdfnotes
  2. docsMIT OCW 16.06 Lecture 32: Discrete Design
  3. docsMathWorks: Control System Design and Tuning

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