Discrete-Time Control, Hold Elements & Sample Rate Choice

A sampled-data loop contains at least two time systems. Software updates sequences indexed by $k$ ; the physical plant evolves for every real $t$ . The interface—anti-alias filter, sampler, ADC, computation, DAC or PWM, and hold—determines how those worlds connect. A controller $C(z)$ designed without that timing contract is incomplete.

Sample acquisition, computation, and actuator update occur at distinct instants. Their separation produces delay and jitter even when the nominal period is fixed.

The timing contract #

For sample period $T_s$ , define precisely:

when the sensor aperture occurs and whether channels are simultaneous;
when ADC data become available;
whether control uses $y[k]$ or the previous sample;
worst-case computation and communication latency;
when the actuator register changes;
what waveform is applied between updates;
what happens on a late, repeated, missing, or invalid sample;
which clock timestamps the measurement and command.

“Runs at 1 kHz” gives only a nominal period. A periodic task that samples at $kT_s$ , completes at $kT_s+\tau_k$ , and updates the actuator then implements a variable delay $\tau_k$ . If sensing and actuation are on different clocks, drift is also part of the model.

Exact zero-order-hold state model #

For

\dot x=Ax+Bu,

with $u(t)=u[k]$ held constant for $kT_s\le t<(k+1)T_s$ ,

x[k+1]=A_dx[k]+B_du[k],

where

A_d=e^{AT_s},\qquad B_d=\int_0^{T_s}e^{A\tau}B\,d\tau.

This is exact at sample instants for the stated zero-order hold. It does not say the intersample state or output is constant. Computing $B_d$ through an augmented matrix exponential is robust even when $A$ is singular:

\exp\!\left(\begin{bmatrix}A&B\\0&0\end{bmatrix}T_s\right) =\begin{bmatrix}A_d&B_d\\0&I\end{bmatrix}.

Forward Euler $A_d\approx I+AT_s$ , $B_d\approx BT_s$ is an approximation with its own stability and accuracy limits. Do not call it exact discretization.

Conversion methods preserve different things #

ZOH is exact at sample instants for piecewise-constant input.
FOH targets piecewise-linear input under the tool's stated convention.
Impulse invariance preserves sampled impulse response but aliases continuous spectral content.
Tustin/bilinear maps the left half-plane inside the unit circle and matches frequency shape approximately; prewarping makes one selected frequency exact.
Matched pole-zero preserves mapped poles/zeros but requires gain and relative-degree handling.

Choose from the physical hold and design objective. A tool default is not evidence that the actuator actually behaves as a ZOH.

Choosing sample rate #

Nyquist's sampling theorem is necessary for signal reconstruction, not a complete control-rate rule. The controller sample rate must also preserve phase margin, relevant plant modes, disturbance rejection, and actuator behavior.

Consider:

desired closed-loop crossover and bandwidth;
fastest plant, actuator, and sensor dynamics the controller can excite;
anti-alias filter transition band and phase;
computation/communication delay and jitter;
measurement and actuator resolution;
CPU load, network scheduling, power, and data cost;
discrete zeros introduced by the sampler/hold;
intersample peaks and constraints.

A common heuristic samples many times faster than crossover, but no fixed ratio is universally safe. Build the complete sampled loop at candidate $T_s$ , include measured delay, and recompute margins and nonlinear behavior.

Delay and jitter consume phase #

A fixed delay $\tau_d$ contributes phase

\phi_d(\omega)=-\omega\tau_d.

Near crossover, even a small time delay can remove the remaining phase margin. A ZOH itself has frequency response

H_{ZOH}(j\omega)=T_s e^{-j\omega T_s/2}\mathop{\mathrm{sinc}}\!\left(\frac{\omega T_s}{2}\right),

up to the chosen normalization. Its low-frequency behavior resembles about half a sample of delay plus magnitude droop.

Jitter makes the delay time-varying. If the algorithm integrates using a fixed $T_s$ while actual intervals vary, its effective gains vary too. Timestamp measurements and use the actual interval where the algorithm permits, or enforce a worst-case timing bound and analyze it as uncertainty. Do not silently switch between those semantics.

Aliasing and anti-alias filtering #

Sampling folds content above $f_s/2$ into the baseband. A software filter after the ADC cannot distinguish an aliased component from a genuine low-frequency component. Anti-alias attenuation must occur before sampling, including sensor and analog front-end response.

Control systems can generate their own out-of-band content through PWM, switching, vibration, quantization, and actuator nonlinearities. Test the sensor spectrum with the controller operating, not only the quiet plant.

The analog filter adds delay and phase in-band. Design it jointly with sampling and the loop rather than assuming “more filtering” is free.

Quantization and finite-word behavior #

An $N$ -bit converter over span $R$ has nominal step $\Delta\approx R/2^N$ , but effective behavior also includes noise, nonlinearity, clipping, reference error, and code timing. Quantization creates dead zones and can sustain limit cycles in otherwise stable recursive controllers.

Fixed-point realization adds:

coefficient and state quantization;
rounding or truncation at each operation;
accumulator overflow or saturation;
scaling tradeoffs between range and resolution;
arithmetic-dependent pole movement;
zero-input limit cycles.

The discrete transfer function assumes infinite precision. Verification must run the actual realization and types.

Controller state and update order #

For a PI example,

I[k]=I[k-1]+K_iT_se[k],\qquad u[k]=K_pe[k]+I[k],

but alternate code may compute $u[k]$ from $I[k-1]$ and update afterward. Both are plausible difference equations and they are not identical. Define:

current versus previous sample use;
derivative filter state and initialization;
saturation before or after state update;
anti-windup feedback timing;
output clamp, slew rate, and manual override order;
state behavior on invalid measurements or disabled output.

Equivalent algebra can produce different code because assignment order creates delays.

Missed samples are a mode transition #

On a missed deadline, possible policies include holding the previous command, applying a safe command, running late, or skipping to the next period. These have different closed-loop consequences. No policy should be invented silently.

Specify one approved behavior and model it. Record deadline misses and sample ages. If control and safety require a hard maximum age, enforce it outside the ordinary controller path.

Bumpless transfer and restart #

Switching manual/automatic, controller versions, gain schedules, or sample rates changes the state interpretation. Bumpless transfer initializes states so the new controller reproduces the current actuator output while respecting constraints. On restart, choose explicitly whether state is restored, reconstructed from measurements, tracked in a shadow controller, or reset to a safe condition.

Restoring stale state after the plant has moved can be worse than reset. Resetting an integral state can create a command step. The correct choice follows from the physical mode and safety contract.

Verification ladder #

Compare exact discrete model with continuous simulation at sample instants.
Inspect intersample output and actuator waveform.
Measure acquisition-to-actuation latency and jitter under worst load.
Verify anti-alias attenuation and sample synchronization.
Run saturation, rate limit, quantization, overflow, and missed-sample cases.
Check margins including hold, filter, and delay.
Exercise startup, restart, mode transfer, sensor failure, and watchdog behavior.
Record target-code timing and bit-exact numerical results.

A digital controller is a hybrid real-time mechanism. Correct equations at nominal sample instants are necessary, not sufficient.