Line Coding: NRZ, Manchester, Scrambling & Clock Recovery

Line coding turns bits into a constrained baseband waveform whose spectrum, transition density, DC balance, and error visibility fit the physical channel. This entry derives those tradeoffs, compares common mappings on one bit sequence, and connects block coding and scrambling to clock recovery and link diagnostics.

Line coding is the contract between a bit stream and a baseband physical channel. It is not source coding, which removes redundancy; not channel coding, which adds redundancy to correct errors; and not pulse shaping, which controls the continuous-time pulse spectrum. A line code chooses the signal levels or transitions that represent bits while making the resulting stream observable by the receiver.

The choice is never aesthetic. A transformer-coupled link rejects DC, a clock-and-data recovery loop needs transitions, an optical intensity link cannot transmit negative power, and a serial protocol needs unmistakable violations or commas. The useful question is therefore not “which code is best?” but “which constraints must the waveform satisfy, and what overhead buys them?”

The channel sets four constraints #

For a symbol interval TbT_b, write the transmitted waveform as

x(t)=∑kakp(t−kTb),x(t)=\sum_k a_k p(t-kT_b),

where the line code determines the level sequence aka_k and the pulse shape p(t)p(t) determines how each level occupies time. Four properties dominate:

DC content
A nonzero long-term mean cannot pass through a transformer or AC-coupled path and consumes headroom in many front ends.
Transition density
Edges provide timing observations. A legal stream with a very long constant run can starve clock recovery even when every bit value is otherwise unambiguous.
Bandwidth
For the same bit rate, forced mid-bit transitions move energy upward and demand more channel bandwidth.
Error and framing visibility
Unused codewords, deliberate violations, and comma patterns let a receiver detect loss of alignment or an illegal line state before a payload checksum does.

These constraints are coupled. Guaranteeing one transition per bit, as Manchester does, solves timing and DC balance but roughly doubles the event rate. Scrambling adds almost no deterministic rate overhead, but replaces a hard run-length guarantee with a statistical one.

One sequence, four different waveforms #

Four line encodings of the bit sequence 10110001 Aligned NRZ-L, NRZ-I, Manchester, and AMI waveforms show where each encoding provides transitions and whether it carries DC. bit NRZ-L NRZ-I Manchester AMI same eight bit cells; high, zero, and low are signal levels 1011 0001 +A−A +A0−A
The same bits produce very different timing evidence and average levels. Manchester guarantees a mid-bit edge; AMI alternates the sign of successive ones and therefore suppresses DC; NRZ variants can remain constant for arbitrarily long legal runs.

The drawing uses one explicit convention: NRZ-L maps 1↦+A1\mapsto +A and 0↦−A0\mapsto-A; NRZ-I toggles on a one; Manchester maps 11 to high-then-low and 00 to low-then-high; AMI maps zero to 00 and alternates the polarity of successive ones. Standards sometimes reverse a polarity or transition convention, so a name alone is not an interoperability specification.

Mapping Timing guarantee DC behavior Nominal signalling cost Useful property Main failure mode
NRZ-L none data-dependent 1 level interval/bit simplest slicer long identical runs starve CDR
NRZ-I edge on every one data-dependent 1 interval/bit polarity inversion does not change the decoded bits long zero runs starve CDR
RZ at least a return within marked symbols often still data-dependent two level intervals/bit clear symbol boundaries wider spectrum
Manchester mid-bit edge every bit balanced per bit two half-bit intervals/bit deterministic clock content about twice NRZ edge bandwidth
Differential Manchester mid-bit edge plus boundary rule balanced per bit two half-bit intervals/bit polarity-insensitive decoding wider spectrum and convention risk
AMI edge/activity only on ones balanced for alternating ones ternary levels bipolar violations can signal errors or substitutions zero runs still need substitution or scrambling

Spectrum follows both the pulse and the data #

For an independent symbol sequence with variance σa2\sigma_a^2, the continuous part of the power spectral density has the form

Sx(f)∝σa2Tb∣P(f)∣2,S_x(f)\propto \frac{\sigma_a^2}{T_b}|P(f)|^2,

with additional spectral lines when the sequence has a nonzero mean or periodic structure. The line code changes the statistics of aka_k; pulse shaping changes P(f)P(f). This is why “NRZ bandwidth” is not one immutable number: rectangular pulses have a sinc-shaped spectrum with infinite sidelobes, while a filtered transmitter trades rise time against occupied bandwidth.

The low-frequency limit is especially important. Unipolar NRZ has positive mean for an equiprobable stream and therefore a DC component. Polar NRZ has zero ensemble mean for balanced random data, but a finite packet can still contain a damaging long run. Manchester cancels within every bit interval, and AMI cancels the contributions of consecutive marks, so both are much safer through AC coupling.

Block codes buy deterministic constraints #

A constrained block code maps kk payload bits into nn line bits. Its raw efficiency is

η=kn,Rline=Rpayloadη.\eta=\frac{k}{n}, \qquad R_{line}=\frac{R_{payload}}{\eta}.

The classic 8b/10b code has η=0.8\eta=0.8: a 1 Gb/s payload requires a 1.25 Gbaud binary line rate before other overhead. Widmer and Franaszek constructed the code around bounded disparity, limited runs, enough code space for control symbols, and an implementation that tracks running disparity. If positive and negative levels contribute +1+1 and −1-1, running disparity is their cumulative sum. The encoder selects a positive- or negative-disparity representation so the sum remains bounded rather than drifting indefinitely.

This state is part of the protocol. Decoding ten bits without the expected running-disparity state can turn a valid symbol into a disparity error. Conversely, invalid code groups, invalid disparity, and comma alignment are powerful link diagnostics: they distinguish an analogue corruption or word-slip from a valid payload that merely fails a higher-layer CRC.

Modern high-rate links often spend less deterministic overhead. 64b/66b carries 64 payload/control bits in a 66-bit block, so η=64/66≈96.97%\eta=64/66\approx96.97\%. The two-bit sync header supplies block alignment and type information; a scrambler whitens the remaining 64 bits. IEEE 802.3 uses this family in multiple PHYs. The important trade is that 64b/66b does not provide the same short absolute run-length bound as 8b/10b: it combines explicit block headers with statistical transition density.

Scrambling is not error correction #

A scrambler XORs the data with a deterministic pseudo-random sequence. The receiver applies the corresponding inverse operation; no user information is intentionally removed or protected. The goals are spectral whitening, transition density, and avoidance of repetitive EMI patterns.

Two architectures have different failure semantics:

Scrambler Receiver state Error propagation Synchronization
synchronous/additive independent PN generator normally one channel error remains one output error transmitter and receiver PN phase must be aligned or reset
self-synchronizing/multiplicative previous received bits drive the inverse filter one channel error can flip the current bit and later tapped bits reacquires after enough correct received bits

For a self-synchronizing polynomial such as 1+D3+D51+D^3+D^5, a single received-bit error affects the descrambler output now and again three and five bits later. That multiplication is bounded, but it matters when sizing bursts for a downstream decoder or CRC.

Clock recovery closes the contract #

A CDR estimates the sampling phase and often the line rate from received transitions. The line code controls how frequently informative phase errors exist; the analogue channel controls how much jitter and ISI those edges carry. The dependency is therefore circular: the code must feed the timing loop, and the loop must sample the code where its constraints are recognizable.

For burst links, the preamble first provides dense, known transitions for acquisition. Payload coding then maintains enough activity for tracking. Block alignment or a comma detector follows, and only then can the receiver interpret code-group validity or disparity. A frame marker placed after an unknown scrambler state is not a usable acquisition aid unless the protocol defines how that state is established.

A worked selection #

Suppose a transformer-coupled serial link must carry 800 Mb/s of payload, recover clock from data, and declare word misalignment locally.

  1. Plain NRZ is rejected: an all-zero payload is legal and provides no transitions.
  2. Manchester satisfies DC and timing, but its half-bit events push the physical signalling activity toward 1.6 G transitions/s.
  3. 8b/10b produces a 1.0 Gbaud line rate, bounds disparity and runs, and provides comma/control symbols plus code/disparity errors.
  4. 64b/66b requires only 800×66/64=825800\times66/64=825 Mb/s before other framing, but its run bound is statistical and its two-bit headers provide weaker local error detection than the constrained 10-bit alphabet.

The correct choice depends on the CDR's tolerance to rare runs and on whether 175 Mb/s of saved line rate is worth giving up 8b/10b's stronger symbol-level observability. That is a measurable PHY trade, not a matter of naming preference.

Diagnose the line in layers #

Symptom First hypotheses Decisive measurement
link loses lock only on idle or repeated payload insufficient transition density; wrong scrambler reset transition-run histogram before the CDR; scrambler state at packet boundary
many disparity errors but few invalid symbols polarity lane error; wrong running-disparity initialization raw 10-bit groups plus encoder/decoder disparity state
CRC bursts with clean code groups analogue ISI/jitter inside legal decision regions; higher-layer framing bathtub/eye scan and block/frame marker position
baseline moves with data pattern AC-coupling time constant too short; code not truly balanced over the required window mean level versus run length and coupling high-pass corner
every symbol is wrong after a reset convention mismatch, bit order, polarity, or scrambler phase compare one known training word at the serializer and decoder boundaries

The complete path to verify is therefore payload bits → block encoder or scrambler → serializer polarity and bit order → channel → CDR → block alignment → inverse mapping → error counters. A line code is working only when both recovered data and its promised constraints survive that path.

Sources

  1. bookSystems for Transmission of Digital Informationpdfnotes
  2. paperA DC-Balanced, Partitioned-Block, 8B/10B Transmission Code
  3. docsTM Synchronization and Channel Coding, CCSDS 131.0-B-5pdfnotes
  4. docsIEEE P802.3bn technical decisions

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