AVR Core, Memory & Instruction Set

The classic 8-bit AVR model is register-rich: thirty-two 8-bit working registers sit next to the ALU, and three register pairs form address pointers. That makes many arithmetic operations regular, but memory-space and device-size boundaries still matter.

Register and status model #

R0–R31 are working registers. R26:R27, R28:R29, and R30:R31 also form the X, Y, and Z pointers. Y and Z support displacement forms on applicable cores. The status register SREG holds carry, zero, negative, overflow, signed, half-carry, transfer-bit, and global-interrupt state.

Some immediate instructions can name only R16–R31 because their opcode must encode both an immediate value and a register in one word. This is not an assembler preference; it is an encoding constraint that influences register allocation.

Program and data spaces #

AVR uses a modified Harvard organization:

• flash holds instruction words and constants read through program-memory instructions;
• the data address space contains working registers, I/O registers, extended I/O, and SRAM in device-defined ranges;
• EEPROM is nonvolatile data storage accessed through a peripheral-like control sequence;
• boot flash may have separate protection and self-programming rules.

The spaces can have overlapping numeric offsets without being interchangeable. LD/ST address data space; LPM/ELPM read program space; I/O instructions reach a compact register window; EEPROM normally requires controller registers rather than ordinary loads.

Address width grows in pieces #

Small devices fit program addresses into Z and calls into compact encodings. Larger devices add state such as RAMPZ for extended program-memory access and may need wider return addresses. The compiler, linker, startup code, interrupt prologue, bootloader, and hand-written assembly must all agree on that device model.

Instruction families #

Many instructions are one word, but some control transfers and immediate data forms are two words. A skip instruction must detect and skip the whole following instruction, so its cycle cost is path- and width-dependent.

Pipeline and observable timing #

Classic AVR overlaps instruction fetch with execution, often allowing one instruction per clock after the pipeline fills. A taken branch disrupts the sequential fetch path. Memory, flash, and core generation can add timing differences.

Cycle counting is appropriate only when interrupts, flash wait behavior, compiler changes, and the exact core are controlled. Peripherals and timers are normally better time references because they turn a timing requirement into explicit clocked state.

Stack and interrupts #

The stack lives in SRAM and grows downward on the ATmega devices covered here. Calls and interrupts push return-address state; software and compiler-generated prologues save any additional registers and SREG state they require. Stack initialization must precede calls or interrupts on devices where reset does not establish a usable application stack automatically.

An ISR is an ABI boundary:

1. hardware establishes the architectural interrupt state and return address;
2. the prologue preserves compiler- or program-required registers and status;
3. the handler services and acknowledges the peripheral source;
4. the epilogue restores state;
5. the interrupt return restores control flow and global interrupt semantics.

Device availability is part of the ISA question #

The family instruction manual lists instructions across AVR variants. A particular MCU may omit multiply, extended load, long call, or other forms. Always assemble for the exact device and let the toolchain reject unavailable opcodes. Then inspect the linked image when range, trampoline, boot-section, or startup behavior matters.

The durable workflow is: use the ISA manual for semantics and encoding, the device manual for availability and memory sizes, and the ABI/toolchain documentation for register ownership and object-level behavior.