PCB Routing, Return Paths & Power Distribution

Every current leaves a source and returns to it. A PCB route is therefore not a trace but a loop whose impedance varies with frequency. At low frequency, resistance and available copper dominate. As edge rate rises, inductance and the electromagnetic field between a conductor and its reference dominate, so return current crowds under the forward path.

Route the loop, not the net name #

Kirchhoff's current law still holds, but “ground” is not an equipotential sink. Copper has resistance and inductance; shared paths convert one circuit's current into another circuit's voltage error:

$$V_{shared}(s)=I(s)Z_{shared}(s).$$

This is why a sensor return should not share a narrow neck with a motor return, and why a switching converter's hot loop must be compact. The goal is not to make every ground separate. It is to give each important current a low-impedance, predictable path and join domains at the actual functional boundary.

For high-frequency signals over a solid plane, continuity is usually best. Plane splits, slots, and voids force return current around the discontinuity, enlarging loop area and increasing both susceptibility and radiation.

Layer transitions must transfer the return #

When a signal changes layer but remains referenced to the same plane, place a nearby ground stitching via so its return can change layer locally. When references change—for example from a ground plane to a power plane—the return needs a nearby high-frequency connection between those references, often a decoupling capacitor whose placement and value support the transition.

Route differential pairs together so the two conductors see similar geometry, but remember that they can still couple to a reference plane and create common-mode current through imbalance. Length matching cannot compensate for a discontinuity, asymmetric via field, or connector pinout.

Power distribution is an impedance problem #

A load step $\Delta I$ causes supply disturbance approximately

$$\Delta V(f)=\Delta I(f)Z_{PDN}(f).$$

If the allowed disturbance is $\Delta V_{max}$, a first design target is

$$Z_{target}=\frac{\Delta V_{max}}{\Delta I_{step}}.$$

The source regulator controls low frequencies; bulk capacitors supply slower load changes; local capacitors and plane capacitance handle faster changes; package and on-die structures dominate at the highest frequencies. Real capacitors include equivalent series resistance and inductance, so capacitance alone does not predict performance.

flowchart TB
  S["Source / regulator"] --> B["Bulk storage"]
  B --> P["Planes and interconnect"]
  P --> L["Local decoupling"]
  L --> K["Package and load"]
  K -- "return current" --> P
  P -- "return current" --> S

Multiple capacitors and planes form resonances. A mixture of values is useful only after accounting for mounting inductance, ESR, tolerances, and the resulting impedance curve. “One of every decade” can create anti-resonant peaks.

Build compact decoupling loops #

A bypass capacitor supplies transient current locally only if the entire loop—power pin, capacitor, reference connection, and package return—is low inductance. Short, wide connections and closely spaced vias matter more than an attractive schematic. Avoid long necks and via arrangements that put the capacitor electrically beyond the load.

Bulk input capacitance at a connector must be evaluated with cable inductance, hot-plug behavior, inrush, source stability, and protection. A large capacitor can reduce droop yet worsen connector arcing or excite an input-filter instability.

Route by constraint class #

Order routes according to how little freedom they have:

1. safety and isolation boundaries;
2. commutating power loops and precision analog feedback;
3. clocks, high-speed serial, controlled impedance, and timing-critical buses;
4. low-level analog and high-impedance nodes;
5. power distribution and high-current paths;
6. ordinary digital control and slow signals.

This is not universal—the actual criticality comes from the requirements—but it prevents easy nets from consuming the geometry needed by constrained ones.

At corners, neck-downs, pads, and vias, judge the full field discontinuity rather than folklore about 45° versus 90°. For ordinary boards, reference continuity, via stubs, connector launches, and impedance changes dominate corner style. Use field-solver or validated rules when controlled impedance matters.

Diagnose current-path failures #

The Analog Devices grounding and decoupling treatments are useful because they explain these behaviors as current paths. A routing rule is trustworthy only when that causal path is understood.