PCB Types, Stackups, Materials & Fabrication

A PCB stackup is an electrical, mechanical, thermal, and manufacturing structure whose copper geometry only works because materials and fabrication processes realize it within controlled tolerances.

budding working of deep confidence: likely planted 2026-08-21 tended 2026-08-21 pcbstackuplaminatesviasfabrication

A printed circuit board is a laminated interconnect structure. Copper forms conductors and reference planes; resin and reinforcement set spacing and mechanical behavior; plated holes connect layers; finishes protect exposed metal; mask and legend support assembly. Every one of these features varies through fabrication, so a stackup must be negotiated with the fabricator rather than guessed in CAD.

Choose a construction for the product #

Construction	Strength	Main constraint
Single-sided	Low cost, simple process	Crossovers and return paths are difficult
Double-sided plated-through	Flexible routing and assembly	Limited plane structure and density
Multilayer rigid	Controlled references, power distribution, density	Lamination registration, via aspect ratio, cost
HDI	Fine pitch, microvias, compact routing	Specialized build-up cycles and capture-pad rules
Flexible	Dynamic or folded interconnect, low mass	Bend mechanics, adhesive/coverlay, stiffener transitions
Rigid-flex	Removes connectors and harnesses	Complex stack transitions and mechanical qualification

Layer count follows interconnect and reference needs, not prestige. A four-layer board with uninterrupted references can outperform a poorly planned eight-layer board.

Read a stackup as a field structure #

flowchart TB
  L1["L1: components and signals"] --- D1["Thin dielectric"]
  D1 --- L2["L2: continuous reference plane"]
  L2 --- C["Core / controlled thickness"]
  C --- L3["L3: power or second reference"]
  L3 --- D2["Thin dielectric"]
  D2 --- L4["L4: signals and components"]

A signal layer close to a continuous plane forms a compact electromagnetic path: the trace carries forward current and the plane carries return current. Dielectric thickness, copper thickness, trace width, resin content, and local copper density determine impedance. Swapping nominally similar laminate or prepreg can change all of them.

Material properties answer different questions:

glass-transition temperature $T_g$ marks a change in polymer mechanical behavior, not decomposition;
decomposition temperature and time-to-delamination relate to assembly heat survival;
in-plane and through-thickness thermal expansion drive plated-hole and component strain;
dielectric constant $D_k$ affects impedance and propagation, while dissipation factor $D_f$ affects dielectric loss;
moisture absorption changes leakage, loss, mass, and reflow vulnerability;
comparative tracking behavior matters to creepage design, but does not replace the applicable safety standard;
peel strength, flexural modulus, and copper type govern mechanical durability.

Datasheet “typical” values may be measured by methods that do not match field geometry or frequency. Controlled-impedance design uses the fabricator's material library, field solver, coupon, and finished-board verification.

How a multilayer board is made #

The exact flow varies, but the causal chain is stable:

Image and etch inner-layer copper.
Inspect and treat copper surfaces for bonding.
Stack cores, prepregs, and foils; laminate under heat and pressure.
Drill mechanical holes; laser-drill microvias where specified.
Desmear and metallize hole walls, then electroplate copper.
Image and etch outer layers.
Apply solder mask, surface finish, and legend.
Route or score the profile; electrically test and inspect.

Each step creates design limits. Drilling creates positional error and smear. Plating needs a manufacturable hole aspect ratio and produces thickness variation. Lamination shifts layers. Etching changes conductor width. Mask registration affects dams. Routing and scoring constrain edge copper and component clearance.

Vias are structures, not ideal nodes #

A plated through via spans the board and is robust but consumes routing area on every layer. Blind and buried vias save area but add lamination sequences. Microvias have shallow aspect ratios and enable HDI escape routing, but stacked structures and copper-filled configurations need a qualified process.

Reliability depends on finished hole diameter, plating thickness and quality, capture pads, annular ring after registration error, resin recession, thermal-expansion mismatch, and the temperature-cycle mission. A CAD rule that only checks nominal annular ring misses the manufacturing distribution.

Copper, finish, mask, and profile #

Copper thickness is altered by base foil and subsequent plating; outer layers often do not equal inner layers. Surface finish affects solderability, contact behavior, planarity, shelf life, wire bonding, and cost. Solder mask is not generally a certified safety insulation barrier unless the product standard and material system explicitly allow it. The final profile includes tolerances, slots, castellations, controlled edges, and keepouts dictated by enclosure and depanelization.

Close the loop with the supplier #

Start with functional needs—impedance, voltage spacing, current, thermal spreading, flex life, finished thickness, flatness, and reliability—then ask candidate suppliers for a buildable stackup and capability distribution. Record material families and allowed substitutions, copper and dielectric targets, via structures, finish, acceptance class, coupons, impedance tolerance, and special inspections in the controlled fabrication package.

The current IPC design family provides general, rigid, flexible, HDI, and current-capacity frameworks. Its role is to establish shared requirements and methods; the actual product still needs a specific stackup and an agreed process capability.