Pulse Waveforms, RC Shaping & Timing

A pulse is not just two levels. Its amplitude, baseline, width, period, duty cycle, rise/fall time, overshoot, ringing, and droop together define what the next stage receives. RC shaping is the controlled charging and discharging of a capacitor between state-dependent boundary conditions.

The universal first-order trajectory #

After a switch changes at $t=0$, a first-order node moves from initial value $v(0^+)$ toward final value $v(\infty)$:

$$v(t)=v(\infty)+\left[v(0^+)-v(\infty)\right]e^{-t/\tau}, \qquad \tau=R_{th}C.$$

$R_{th}$ is the resistance seen by the capacitor with independent sources zeroed in that switch state. Capacitor voltage cannot jump without an impulse current, so $v(0^+)=v(0^-)$ in an ordinary finite-energy circuit.

flowchart TB
  STATE["choose switch state"] --> FINAL["find v(∞)"]
  STATE --> RTH["find Rth seen by C"]
  PREV["carry vC(0-) across edge"] --> SOLVE["exponential trajectory"]
  FINAL --> SOLVE
  RTH --> SOLVE
  SOLVE --> NEXT["next edge or threshold crossing"]

This method is safer than memorizing separate formulas for every timing circuit.

Differentiating and integrating limits #

For a high-pass RC network observed across the resistor, $\tau\ll t_p$ produces short edge pulses: the capacitor passes rapid change, then the output decays toward zero. It is an approximate differentiator only over a band where $\omega RC\ll1$ and source/load impedances preserve the assumed topology.

For a low-pass RC network observed across the capacitor, $\tau\gg t_p$ makes output change little during one pulse, approximating integration or averaging. It is not an ideal mathematical integrator at DC; leakage and finite resistance establish a final value.

Pulse distortion metrics #

• Rise time is commonly measured from 10% to 90%; a one-pole response has $t_r\approx2.2\tau$.
• Droop is the loss of a nominal flat top caused by AC coupling or finite storage.
• Overshoot and ringing expose underdamped poles, transmission mismatch, or probe/layout resonance.
• Baseline wander appears when an AC-coupled signal's average or duty cycle changes.
• Jitter is timing variation; it cannot be inferred from voltage noise alone without the threshold slew rate.

Loading and cascading #

The next stage changes $R_{th}$ and therefore $\tau$. Cascading nominal RC sections is not equivalent to multiplying independent transfer functions unless each is buffered. Likewise, a probe capacitance can lengthen a fast node's time constant enough to hide the fault being measured.

Design by specifying the waveform property to preserve or reject, deriving the required pole/zero, including source/load, then checking peak current and threshold margins. For precise timing, use a comparator and defined reference rather than relying on a logic input's undocumented switching point.