Computer Electronics: Pulse Electronic Devices (KPI, 2011)
A 208-page lecture text on pulse metrics, RC waveform shaping, semiconductor switches, bistable and monostable circuits, comparators, ramp generators, and resistor-network DACs. It supplies analyzable timing mechanisms rather than current component guidance.
This second volume treats pulse electronics as controlled movement between nonlinear states. Its reusable core is the timing argument: identify the switch state, replace the nonlinear element by the appropriate on/off model, solve the capacitor or inductor trajectory, and determine the next threshold crossing. That method unifies clippers, transistor switches, Schmitt triggers, monostables, astables, and ramp generators.
Coverage #
| Lecture | Printed pages | Durable subject |
|---|---|---|
| 7 | 9–45 | Pulse amplitude, duration, rise/fall time, duty cycle, droop and overshoot; passive and active RC differentiators/integrators |
| 8 | 46–75 | Diode and thyristor switches; serial and shunt limiters; biased clippers |
| 9 | 76–101 | BJT switching, storage delay, saturation, clamping, and faster switching variants |
| 10 | 102–138 | Bistables, monostables, and Schmitt-trigger thresholds |
| 11 | 139–173 | Comparator level formation, multivibrators, linear ramps, triangle and sawtooth generators |
| 12 | 174–206 | Binary-weighted, R–2R, current-steering, serial, and integrated DAC structures |
Engineering contribution #
The source repeatedly separates waveform specification from circuit realization. A pulse is not merely high or low: finite rise time, droop, baseline shift, overshoot, ringing, duty cycle, and repetition period determine whether the next stage interprets it correctly. Likewise, a switch has propagation, charge-storage, drive, and recovery costs. These distinctions are preserved in GTK and generalized from the source's BJTs and diodes to modern CMOS logic, MOSFET switches, comparators, and mixed-signal interfaces.
The DAC chapters expose the central trade: binary weighting is conceptually direct but demands a wide resistor ratio range; an R–2R ladder uses only two values and scales better; segmented and current-steering architectures trade area and decoding for monotonicity, speed, and glitch control. Named legacy converter ICs are not used as present-day design examples.
Limits #
- Saturated BJT switching dominates the examples, while current systems often use CMOS gates, MOSFETs, dedicated comparators, and integrated timing blocks.
- Parasitic inductance, transmission-line behavior, ground bounce, metastability, and EMC are outside the low-frequency lumped treatment.
- The DAC discussion predates current converter interfaces, calibration, dynamic specifications, and integrated references.
- Several computed examples depend on idealized thresholds and output levels; real limits come from the selected device's datasheet over process, supply, temperature, and load.
Visual audit #
All 208 rendered pages were inspected. Load-bearing visuals include annotated pulse shapes, exponential capacitor trajectories, piecewise switch equivalents, limiter transfer curves, multivibrator timing diagrams, comparator hysteresis loops, sawtooth-generation waveforms, and DAC ladder/current-switching schematics.
GTK redraws timing and state-transition visuals because the source's multi-panel scans become unreadable at article width. The new diagrams preserve which threshold causes each transition, the capacitor's charge/discharge direction, and the causal relationship between input, state, and output. Circuit-specific legacy implementations are summarized by their state equations rather than copied. No original raster was retained: the essential information is topology and timing, both clearer in theme-aware vector or Mermaid form. Decorative repetition and pages that only enumerate part-number pinouts were omitted.