Transistor Amplifiers, Biasing & Small-Signal Models

An amplifier uses a supply to create a larger replica of a signal. The signal does not supply the output energy; it controls how the active device routes supply energy into the load. Correct design therefore starts with the DC operating point and available headroom, then linearizes the device for the intended signal range.

DC first, AC second #

Bias analysis finds the quiescent point $Q$ with the signal set to zero. Coupling and bypass capacitors are open for DC. Once $Q$ is known, small changes are analyzed with a small-signal model in which DC supplies are AC ground and sufficiently large capacitors are shorts over the frequency band of interest.

flowchart TB
  DC["DC bias network"] --> Q["operating point Q<br/>current, voltage, temperature"]
  DEV["nonlinear device"] --> Q
  Q --> LIN["local linearization<br/>gm, rπ or source resistance, ro"]
  LIN --> AC["gain + Zin + Zout + bandwidth"]
  AC --> CHECK["verify signal swing stays near Q"]

This separation is conditional: if the signal moves the device far enough that parameters vary substantially or a junction changes region, the small-signal answer no longer predicts the waveform.

Core stages #

For a BJT common-emitter stage with an AC collector load $R_L'$ and unbypassed emitter resistance $R_E$,

$$A_v \approx -\frac{g_mR_L'}{1+g_mR_E}.$$

The minus sign is inversion. Emitter degeneration reduces gain but stabilizes it against $g_m$ and $\beta$, raises input resistance, improves linearity, and increases usable signal range. A bypass capacitor can restore AC gain above its corner while retaining DC stabilization, creating a deliberate low-frequency pole.

A common-source FET stage is analogous. An emitter/source follower has gain near one but transforms impedance, making it a buffer. A differential pair steers an approximately fixed tail current between two branches; it responds to input difference while rejecting common movement to the extent allowed by matching and tail-source impedance.

Gain is not the only specification #

An amplifier must close simultaneously on:

• input and output impedance, including source and load interaction;
• signal swing before cutoff, saturation, current limiting, or output clipping;
• bandwidth from coupling/bypass capacitors, device capacitances, and Miller effect;
• noise from source resistance, device current, and bias network;
• distortion from changing transconductance and load;
• power dissipation and junction temperature;
• bias spread across device, supply, and temperature.

The overall voltage gain from source to load includes both dividers:

$$\frac{v_L}{v_S}=\frac{Z_{in}}{R_S+Z_{in}}\,A_v\,\frac{Z_L}{Z_{out}+Z_L}.$$

Quoting unloaded stage gain alone can therefore be meaningless.

Bias that survives reality #

For a BJT, a resistor divider feeding the base plus emitter degeneration is usually more predictable than a single base resistor. Design the divider current and Thevenin resistance so base-current variation does not move $Q$ excessively, then check worst-case $\beta$, $V_{BE}$, leakage, supply, and resistor tolerance. For FETs, threshold spread is similarly too broad to support a “typical-value” bias without feedback.

Debugging sequence #

Measure DC node voltages first. If $Q$ is wrong, an AC waveform is evidence of the wrong circuit. Then inject a small known signal, verify gain and phase stage by stage, and only then increase amplitude to find the first region boundary. Unexpected high-frequency oscillation points to the feedback path formed by device capacitance, layout, supply impedance, and probing — not to the low-frequency gain equation.