Power-Converter Harmonics, Protection & Thermal Design

Nominal power says little about converter stress. The switch waveform determines semiconductor loss and EMI; the load and source determine low-order harmonics; protection delay determines fault energy; and the thermal path determines junction temperature and life. These are coupled: slowing an edge may reduce ringing but increase switching loss, while raising carrier frequency may improve current ripple but heat semiconductors and magnetics.

Two different harmonic problems #

Low-frequency harmonics arise from the conversion pattern. A diode-capacitor front end draws narrow line-current pulses; a six-pulse bridge produces characteristic current harmonics; inverter modulation produces fundamental plus sidebands. They affect RMS current, transformer and motor heating, torque ripple, and grid voltage distortion.

High-frequency electromagnetic interference comes from large $dv/dt$ and $di/dt$ acting through parasitic capacitance and inductance. Differential-mode current circulates in intended conductors; common-mode current returns through chassis, heat sinks, cable shields, bearings, isolation capacitance, and protective earth. A filter schematic is meaningless without these return paths and impedances.

IEC 61000-3-12 limits harmonic currents for equipment above 16 A and up to 75 A per phase on covered public low-voltage systems. IEC 61800-3 is the product EMC standard for power-drive systems. Applicability, environment, installation, and test conditions must be established before quoting a limit.

Protection layers #

A fuse can limit catastrophic fault energy but may be too slow for semiconductor short-circuit protection. A gate-driver trip can save a switch but does not isolate the source. Each layer has a different job and must be coordinated.

From loss to junction temperature #

For steady conditions, a simplified series thermal path gives

$$T_j=T_a+P(R_{\theta JC}+R_{\theta CS}+R_{\theta SA}),$$

where the terms are junction-to-case, case-to-sink, and sink-to-ambient thermal resistance. Parallel heat paths and time-varying power need a thermal network or manufacturer transient-impedance curves.

Thermal capacitance makes short pulses different from continuous loss, but repeated pulses accumulate. Power cycling also fatigues bonds, solder, substrates, and interfaces even when peak junction temperature stays legal; temperature swing and dwell matter to lifetime.

Layout, damping, and measurement #

Reduce commutation-loop inductance before adding a snubber. Place film or ceramic DC-link decoupling at the switching module, use Kelvin gate and current-sense connections, and keep switch-node copper away from quiet sensing. Then size RC/RCD/TVS or active clamps from measured energy and ringing, not from a probe trace corrupted by a long ground lead.

Measure differential and common-mode quantities with probes rated for working voltage and $dv/dt$. Verify probe loop, bandwidth, deskew, and loading. Correlate electrical loss with case, heat-sink, coolant, inductor, transformer, and capacitor temperatures after real thermal settling.

Verification matrix #

Cover minimum/maximum line, light/full/overload, all power-flow directions, cold/hot start, carrier extremes, current limit, regenerative braking, fan failure, clogged filter, phase loss, sensor fault, short circuit, ground fault, surge, and repeated restart. Record spectra, peak and RMS currents, switch overshoot, gate margin, protection latency, DC-link trajectory, and thermal steady state. The assembled converter—not the spreadsheet—must demonstrate the declared envelope.