Power-Semiconductor Switches & Switching Losses

A power semiconductor is useful because it approximates a controlled switch while handling voltage and current that the controller cannot. It is never an ideal switch: the on-state dissipates power, transitions dissipate energy and excite parasitics, the off-state leaks and has a finite blocking limit, and the junction stores heat. Selection is therefore a waveform-and-fault problem, not a comparison of headline amperes.

Device families #

These are tendencies, not substitution rules. Package inductance, reverse conduction, short-circuit withstand, gate limits, avalanche behaviour, isolation, cooling, cost, and qualification can reverse a simplistic technology ranking.

Loss belongs to the actual waveform #

Conduction loss is the average of instantaneous device voltage times current. For a MOSFET approximation,

$$P_{cond}=I_{rms}^{2}R_{DS(on)}(T_j).$$

For an IGBT approximation $v_{CE}=V_0+r_Ci$,

$$P_{cond}=V_0I_{avg}+r_CI_{rms}^{2}.$$

Datasheet switching energies $E_{on}$ and $E_{off}$ are measured at stated voltage, current, gate resistance, temperature, and commutation loop. A first estimate is

$$P_{sw}=f_s(E_{on}+E_{off}),$$

then corrected with manufacturer guidance for the real operating points. Add diode reverse-recovery, gate-drive, output-capacitance, dead-time, snubber, and magnetic losses where applicable.

The gate is a current loop #

The controller supplies logic; the gate driver sources and sinks charge through a physically small high-di/dt loop. Turn-on and turn-off resistances set edge rate, switching loss, overshoot, and EMI. High-side devices need a referenced or isolated supply; bootstrap supplies impose startup and duty-cycle limits. Undervoltage lockout must hold the switch in a defined off state while the driver rail is invalid.

Fast drain-voltage transitions push displacement current through gate-drain capacitance. If the off-state path is too inductive or resistive, gate voltage can cross threshold and create shoot-through. A close Miller clamp or negative off bias provides a lower-impedance path, but only the measured worst-case gate waveform proves immunity. Dead time prevents commanded overlap; excessive dead time increases diode conduction, distortion, and loss.

Ratings that must be read together #

• Repetitive blocking voltage needs margin for measured overshoot, not only nominal bus voltage.
• Pulsed and continuous current ratings assume specified case temperature and thermal path.
• Safe operating area constrains simultaneous voltage and current during linear operation, short circuit, or slow switching.
• Maximum gate voltage is an absolute damage boundary; recommended drive voltage is a different specification.
• Junction-temperature limits do not guarantee package, bond-wire, solder, or insulation life under cycling.
• $dv/dt$, $di/dt$, reverse recovery, avalanche, and short-circuit withstand are circuit-dependent limits.

Selection workflow #

Define every normal and fault switching state; obtain device voltage, average/RMS/peak current, reverse current, switching frequency, and temperature range; estimate losses with temperature iteration; design the gate and commutation loops; verify safe operating area and protection timing; build the thermal network; and measure double-pulse or representative converter waveforms with low-inductance probing. The best switch is the one whose complete operating envelope closes with margin, not the one with the smallest single datasheet number.