Power-Converter Modeling & Feedback-Loop Design

A converter schematic describes switching states, not one time-invariant plant. Control design needs a model that preserves the slow evolution of inductor currents and capacitor voltages while discarding switching ripple. The disciplined path is switch-state equations → averaged nonlinear model → operating point → small-signal model → transfer functions → loop design → measured verification.

Begin with state equations, not a memorized transfer function #

Let the energy-storage state be $x$—typically inductor currents and capacitor voltages—and let $u$ contain source and load disturbances. For two switch configurations,

$$\dot{x}=A_1x+B_1u \quad \text{and} \quad \dot{x}=A_2x+B_2u.$$

If state ripple is small during one switching period and configuration 1 occupies fraction $d$, first-order state-space averaging gives

$$\dot{\bar{x}}=[dA_1+(1-d)A_2]\bar{x}+[dB_1+(1-d)B_2]\bar{u}.$$

This equation is generally nonlinear because $d$ multiplies states and inputs. It is a large-signal envelope model: it can describe startup or a duty transient only while its assumed topology and conduction mode remain valid.

Solve the equilibrium before perturbing it #

Write each quantity as a quiescent value plus a small perturbation:

$$x=X+\hat{x},\qquad u=U+\hat{u},\qquad d=D+\hat{d}.$$

The operating point satisfies $0=A(D)X+B(D)U$. Substituting the perturbed quantities and discarding products such as $\hat{d}\hat{x}$ produces a linear model,

$$\dot{\hat{x}}=A\hat{x}+B_u\hat{u}+B_d\hat{d},\qquad \hat{y}=C\hat{x}+E_u\hat{u}+E_d\hat{d}.$$

Laplace transformation then gives plant functions such as control-to-output $G_{vd}(s)=\hat{v}_o/\hat{d}$, line-to-output $G_{vg}(s)=\hat{v}_o/\hat{v}_g$, output impedance $Z_o(s)=-\hat{v}_o/\hat{i}_{load}$, and input impedance $Z_{in}(s)=\hat{v}_g/\hat{i}_g$. They are different questions answered by the same state model.

Buck example #

For an ideal CCM buck with states $i_L,v_o$,

$$L\dot{i}_L=dV_g-v_o,\qquad C\dot{v}_o=i_L-\frac{v_o}{R}.$$

Equilibrium gives $V_o=DV_g$ and $I_L=V_o/R$. The duty-to-output plant is

$$G_{vd}(s)=\frac{V_g}{LCs^2+(L/R)s+1}.$$

The denominator is the damped output-filter resonance. Capacitor ESR adds a zero; inductor resistance, switch loss, sampling, delay, and the load law change the real plant. Deriving the ideal form first is useful because each added term then has a physical origin.

Poles and zeros describe causal behavior #

A left-half-plane pole adds lag and stores energy. A left-half-plane zero can add phase lead. A right-half-plane (RHP) zero adds gain like a zero but phase lag like a pole: the output initially moves opposite the eventual command.

In a CCM boost converter, increasing duty lengthens the interval in which the inductor is disconnected from the output. Output delivery initially falls, then rises after the inductor current has increased. This two-step energy path creates the RHP zero. No compensator can cancel its nonminimum-phase causality robustly; crossover must remain well below it across the complete line/load range.

Assemble the complete loop gain #

For a voltage loop,

$$T(s)=G_c(s)\,G_m(s)\,G_{vd}(s)\,H(s),$$

where $G_c$ is the compensator, $G_m$ the PWM or command gain, $G_{vd}$ the power stage, and $H$ the sensor path. Closed-loop reference tracking is proportional to $T/(1+T)$; source and load disturbances are reduced by $1/(1+T)$ only where loop gain is large and the loop remains stable.

Design from requirements rather than from a preferred compensator:

1. derive or measure the plant at line/load/mode corners;
2. identify the lowest resonance, RHP zero, sampling/delay constraint, and noise-sensitive region;
3. choose crossover below the first non-negotiable phase-loss boundary;
4. place compensator zeros to supply needed phase and low-frequency gain, then poles to roll off noise and switching ripple;
5. calculate gain and phase margins for every plant corner, not only nominal values;
6. verify reference, line, and load transients against voltage/current limits.

Phase margin alone is not a transient specification. A loop with acceptable nominal phase margin may still violate overshoot, settling, current-limit, or mode-transition requirements.

Current-programmed control changes the plant #

Peak-current-mode control closes a fast inner current loop: the control signal requests a peak current and the switch turns off when the sensed ramp reaches it. At low frequency this removes one energy-storage dynamic from the outer voltage loop and often makes compensation simpler. It also introduces sampled switching-cycle behavior, current-sense noise sensitivity, leading-edge blanking, and possible subharmonic oscillation. Artificial slope compensation changes the inner-loop dynamics and must be included in the model.

Average-current control instead regulates a filtered current with a continuous compensator. It is useful when current waveform accuracy matters, such as power-factor correction or bidirectional conversion, but it creates two deliberately separated loops whose bandwidths and limits must be coordinated.

Measure the loop without destroying its bias #

Inject a small AC perturbation at a point where the loop can be separated for AC while its DC bias remains closed. Measure the response on both sides of the injection and form their ratio using the analyzer's convention. The injection transformer or isolator must cover the frequency range, the injected amplitude must remain linear but above noise, and the injection impedance must not materially load either side.

Confirm the operating point before every sweep: input voltage, load, temperature, conduction mode, PWM frequency, and protection state. Repeat at corners, and compare measured plant/loop features with the model. A displaced resonance usually points to component value or load-law error; unexplained phase loss points to delay, sampling, hidden poles, or measurement loading.

A model-completion checklist #

Simulation is strongest after this chain is explicit. A switching simulation checks ripple, commutation, sampled behavior, and limits; an averaged simulation accelerates slow envelope and loop studies. Agreement between two incomplete models is not hardware verification.