Resonant Converters & Soft Switching

Resonant tanks shape current and voltage so semiconductor transitions can occur at zero voltage or zero current. The benefit exists only inside a load-, gain-, frequency-, timing-, and parasitic-dependent commutation region that must be designed and measured.

Hard switching commands a semiconductor transition while it still carries current or blocks voltage, forcing voltage-current overlap and charging or discharging device capacitances dissipatively. A resonant or auxiliary commutation network instead moves charge and current before the gate transition. Zero-voltage switching (ZVS) and zero-current switching (ZCS) are therefore timed boundary conditions, not marketing properties that a topology possesses at every operating point.

Hard switching compared with ZVS and ZCS Three panels show voltage and current at a switching instant. Hard switching has simultaneous voltage and current overlap, ZVS commutates voltage to zero before turn-on, and ZCS commutates current to zero before turn-off. The terminal condition must be ready before the gate transition Hard turn-on gate transition v i v × i overlap → loss Zero-voltage turn-on gate after v ≈ 0 v i tank current moves node charge Zero-current turn-off gate after i ≈ 0 v i tank trajectory removes current hard-switching overlap energy current voltage
Soft switching means the relevant terminal variable has reached its commutation boundary before the controlled transition. The shaded hard-switching overlap represents energy that must be dissipated or recovered elsewhere.

What hard switching dissipates #

During a hard turn-on, a switch can simultaneously support substantial vDSv_{DS} and conduct rising iDi_D, while its output capacitance is discharged and the complementary diode undergoes reverse recovery. A rough constant-capacitance estimate is

EC≈12CossV2,E_C\approx \tfrac12 C_{oss}V^2,

but real CossC_{oss} is nonlinear; use datasheet EossE_{oss} or QossQ_{oss} at the actual voltage. Inductive parasitics add overshoot through v=L di/dtv=L\,di/dt, and recovered diode charge adds current and loss. Raising frequency multiplies each transition energy by transitions per second.

ZVS and ZCS are different commutation goals #

Zero-voltage switching (ZVS)
The commutation network drives switch voltage to approximately zero before turn-on. This primarily avoids dissipative output-capacitance discharge and can reduce diode-recovery stress.
Zero-current switching (ZCS)
The network drives device current to approximately zero before turn-off or commutation. This reduces current-voltage overlap and is especially relevant to devices or rectifiers with costly current tail/recovery behavior.

Neither condition means lossless switching. Gate charge, conduction loss, circulating current, magnetic loss, residual voltage/current, dead-time diode conduction, and auxiliary-network loss remain.

For ZVS, the available commutation current during dead time must move the switch-node charge:

∫t0t0+tdicomm(t) dt≥Qnode.\int_{t_0}^{t_0+t_d} i_{comm}(t)\,dt \ge Q_{node}.

A complementary energy screen is

12LcommIcomm2≳Enode,\tfrac12 L_{comm}I_{comm}^2 \gtrsim E_{node},

where EnodeE_{node} includes the nonlinear output-capacitance energies that must be exchanged. These are necessary scale checks, not substitutes for the full resonant trajectory and device model.

The resonant tank establishes the trajectory #

For a simple lossless series LCLC tank,

ω0=1LC,Z0=LC.\omega_0=\frac{1}{\sqrt{LC}},\qquad Z_0=\sqrt{\frac{L}{C}}.

ω0\omega_0 sets the natural time scale and Z0Z_0 relates tank voltage to current. Load and rectifier action add damping and piecewise topology changes. The quality factor therefore depends on how the load is reflected into the tank, not merely on LL and CC.

The first-harmonic approximation replaces the switching bridge and rectifier waveforms with their fundamental components. It is useful near resonance when tank filtering makes current nearly sinusoidal, but it becomes weak when harmonics, dead time, discontinuous intervals, nonlinear capacitance, or far-from-resonance operation dominate. Time-domain mode analysis or switching simulation must close those regions.

Series, parallel, and LLC behavior #

Tank Useful tendency Design burden
series resonant DC-blocking series capacitor; current naturally falls with open load gain and circulating current vary strongly with frequency/load
parallel resonant load is coupled across a tank branch; can maintain voltage gain over some conditions tank current may circulate even at light load
LLC resonant LrCrL_rC_r plus magnetizing LmL_m widens the usable gain/ZVS region and integrates transformer parasitics deliberately nonlinear gain surface, mode boundaries, light-load ZVS, frequency range, and synchronous-rectifier timing

An LLC converter commonly regulates by switching frequency. Around its intended region it can achieve primary-side ZVS and secondary-side ZCS, but moving above or below resonance changes gain, circulating current, and rectifier commutation. TI's current analysis explicitly identifies non-ZVS boundaries; practical control must prevent operation from drifting into them.

Soft-switching families #

Quasi-resonant switch cells add a resonant inductor/capacitor around a PWM cell so one transition follows a resonant arc. Multi-resonant cells include additional parasitic capacitances in the intended trajectory. Phase-shifted full bridges use leakage or added inductance and device capacitance to commutate bridge nodes. Active-clamp converters recycle leakage/magnetizing energy and reset transformer flux while creating a ZVS opportunity. Auxiliary resonant commutated poles add a controlled path that prepares the main switch node.

Each method trades switching loss for some combination of circulating current, extra RMS conduction, higher peak stress, added devices, control complexity, restricted conversion ratio, and auxiliary loss. The correct comparison is total loss and stress over the mission profile, not nominal turn-on loss alone.

Design the operating region, not one point #

  1. define input, output, load, temperature, startup, burst, overload, and bidirectional ranges;
  2. select the tank and transformer ratios from gain and frequency constraints;
  3. map gain, RMS/peak currents, ZVS/ZCS boundaries, and device stresses over the entire range;
  4. use nonlinear CossC_{oss}/QossQ_{oss}/EossE_{oss}, diode recovery, leakage, magnetizing current, winding capacitance, and dead time;
  5. check magnetic flux balance, core/copper loss, insulation, and rectifier commutation;
  6. include controller frequency clamps, startup sequencing, synchronous-rectifier timing, burst transitions, and fault states;
  7. verify calculated loss against calorimetry or electrical loss partitioning and temperature rise.

Oscilloscope proof #

For primary ZVS, capture each gate voltage, switch-node or vDSv_{DS}, and resonant/primary current with sufficient bandwidth and deskew. The node must reach the intended rail and the body diode or channel establish the correct current direction before gate turn-on; excessive dead time can regain ZVS while increasing diode conduction and reverse-recovery loss. For secondary ZCS, observe rectifier current crossing zero relative to commutating voltage and synchronous gate timing.

Repeat at minimum/maximum input, minimum load before burst, rated load, overload approach, hot and cold device conditions, and each frequency clamp. Record ringing and peak voltage as well as the nominal zero crossing. A single clean waveform at rated load proves one operating point only.

Failure signatures #

Observation Likely mechanism to test
switch node has not reached the rail before turn-on insufficient commutation current/energy, dead time too short, CossC_{oss} larger than modeled
long body-diode interval before gate dead time too long or frequency/load command misplaced
ZVS lost first at light load magnetizing/tank current insufficient; burst or auxiliary commutation needed
high RMS current despite low switching loss operation too far from resonance or excessive circulating energy
secondary voltage spike leakage inductance, rectifier recovery, winding capacitance, or timing error
flux walk or asymmetric current unequal drive timing, DC bias, sensing/control asymmetry, or reset failure

Soft switching is complete only when the commutation boundary, total loss, device stress, magnetic behavior, and controller transitions are all verified over the same operating envelope.

Sources

  1. bookFundamentals of Power Electronics, Second Editionpdfnotes
  2. paperTI SLLA498 — Power Topology Considerations for Solar String Inverters and Energy Storage Systems
  3. paperTI SLUA733 — LLC Analysis Method
  4. docsTI SLLA644 — Bidirectional Isolated DC/DC Resonant Topologies
  5. codeTI TIDM-RESLLC-DCDC — Resonant LLC DC/DC Reference Design

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