Electronic Switches, Clamps & Level Shifting

An ideal switch is zero ohms on and infinite ohms off. A real semiconductor switch has on-voltage or on-resistance, leakage, capacitance, stored charge, finite transition time, control-current requirements, and absolute limits. Those nonidealities matter most exactly when a schematic changes state.

Piecewise topology #

Analyze a diode, BJT, MOSFET, or analog switch by proposing a state, solving the resulting linear circuit, and checking that voltages/currents are consistent with the state. If not, choose another state. This state-consistency method handles series switches, shunt switches, biased clippers, clamps, and level translators.

Saturation versus speed #

Driving a BJT deeply into saturation reduces on-voltage but stores excess charge, increasing storage delay at turn-off. A Baker clamp or Schottky clamp prevents deep saturation where speed matters. A MOSFET avoids minority-carrier storage but still needs a low-impedance gate loop and may conduct through its body diode or reverse channel.

Level shifting is about domains #

flowchart LR
  A["source domain<br/>VOH/VOL, current, power state"] --> X["translator<br/>direction + topology"]
  X --> B["destination domain<br/>VIH/VIL, clamps, power state"]
  A -. "ground offset / common mode" .-> B

A valid translator must meet destination thresholds at worst-case source output levels and currents. It must also tolerate the common-mode difference, edge rate, direction, startup sequence, and case where one side is unpowered. Internal ESD diodes can back-power an unpowered rail through an input unless the datasheet guarantees partial-power-down behavior or external current limiting prevents it.

Open-drain/open-collector translation relies on a pull-up in the destination domain. Rise time is approximately set by pull-up resistance and bus capacitance, while low-level voltage and current are set by the sinking device. It is naturally bidirectional only for protocols whose participants release the line; push-pull buses require explicit direction or an approved auto-direction architecture.

Transient closure #

At fast edges, trace inductance and capacitance form a distributed network. Clamp current path length, return geometry, package inductance, and destination capacitance determine overshoot and ringing. Measure at the receiver pin with an appropriate probe, not only at the source. If edge time is short relative to interconnect delay, use signal-integrity reasoning rather than lumped switch equations.