AVR Instruction Set Manual (Microchip, 2024)

This 147-page manual is the current primary reference for AVR instruction semantics. It separates mnemonic syntax, operation, operands, affected SREG flags, opcode pattern, word width, and cycle count. Device manuals remain necessary because not every AVR core implements every listed instruction and timing may vary by core generation.

Durable model #

The useful way to read the catalogue is by data path:

• register-register ALU operations transform values and selected status flags;
• immediate instructions target the upper register subset because of encoding space;
• load/store instructions route through direct, displacement, pre-decrement, or post-increment address generation;
• program-memory loads route through Z, sometimes extended by RAMPZ;
• relative and absolute control transfers trade encoding width against reach;
• skip instructions make time depend on the width of the skipped instruction;
• bit and I/O operations address compact architectural windows rather than arbitrary memory.

This organization explains why compiler output looks the way it does and why an opcode that exists in the family manual can still be unavailable on a particular device.

Visual audit #

All 147 pages were rendered and inspected. The information-bearing visuals are the instruction-set summary tables, addressing diagrams, opcode bit layouts, and per-instruction flag equations. GTK retains one independent operand-routing diagram and a compact effects table. It does not reproduce the opcode catalogue; exact encoding and flag work remains linked to this primary source.

Operational cautions #

• Cycle counts are part of a core-and-memory implementation, not a promise transferable to every AVR.
• SREG effects matter even when an instruction's destination value is correct; later branches may consume the flags.
• Read-modify-write and skip sequences can be unsafe around interrupts or asynchronous peripheral state.
• Linker relaxation, trampolines, and startup code may choose instructions whose range and availability depend on the selected MCU.