Combinational Logic Circuits

A combinational circuit has no intentional memory: once inputs settle, outputs settle to a Boolean function of those inputs. Internal gates still have delay, so during transitions the output can briefly depend on path history. The distinction is architectural, not a claim of instantaneous behavior.

Reusable structures #

Analysis and synthesis #

To analyze, identify each internal signal, derive its Boolean expression, and compose to the outputs. To synthesize, start from the required truth table or equations, minimize where useful, select a structure, then verify all legal and illegal inputs.

flowchart TB
  SPEC["behavior + legal inputs"] --> TABLE["truth table / equations"]
  TABLE --> MIN["minimize or factor"]
  MIN --> ARCH["MUX / decoder / arithmetic / LUT"]
  ARCH --> TIME["delay + hazards + fan-out"]
  TIME --> VERIFY["equivalence + electrical verification"]

A $2^k$:1 multiplexer can realize any function of $k+1$ variables by using $k$ variables as selects and wiring each data input to 0, 1, the remaining variable, or its complement. A decoder produces minterms; OR selected outputs to form a sum of products. A ROM or LUT makes the same idea explicit as stored configuration.

Priority and enable semantics #

An ordinary encoder assumes one asserted input. A priority encoder defines which wins when several are active and usually exposes a valid/group signal. Decoder and multiplexer enables may be active-high or active-low and may force outputs high, low, or high-Z when disabled. Those states are part of the function, not packaging trivia.

Delay and glitches #

Ripple carry is simple but delay grows with width. Carry-lookahead, prefix, or dedicated FPGA carry structures reduce the critical path. Reconvergent paths can glitch even if the final Boolean value is correct. Register outputs before external use or design hazard-free logic when the consumer is asynchronous, edge-sensitive, or analog.

Verification #

Exhaustively test small input spaces; use formal equivalence or assertions for larger ones. Check propagation across minimum/maximum process, voltage, temperature, and load; decode overlap; output contention; invalid-code behavior; and reset/power-up interactions. Boolean simulation with zero delay proves the mapping but not the circuit.