Flip-Flops, Registers, Counters & Clocked State

Sequential logic adds state: output depends on present input and stored history. Clocking creates a contract about when state may change. The contract fails if data changes too close to the sampling event, clock quality is poor, or asynchronous reset/control is released without timing discipline.

Storage elements #

An SR latch is cross-coupled feedback with set and reset inputs; one input combination is forbidden or implementation-dependent. A D latch removes that ambiguity by deriving complementary internal drive from one data input and is transparent while enable is active. An edge-triggered D flip-flop samples at a clock edge and holds between edges.

JK and T flip-flops express toggle behavior useful for conceptual counter design. Modern synchronous design normally uses D flip-flops and puts the desired next-state logic in front of them:

$$Q_{next}=F(Q,input).$$

flowchart TB
  IN["inputs"] --> NEXT["combinational next-state logic"]
  Q["current state Q"] --> NEXT
  NEXT --> FF["D flip-flops<br/>sample on clock edge"]
  CLK["clock"] --> FF
  FF --> Q
  Q --> OUT["output decode"]

Timing contract and metastability #

Data must be stable for setup time before and hold time after the active edge. Clock-to-Q plus combinational maximum delay plus next register setup must fit the clock period, including skew and uncertainty. Minimum path delay must satisfy hold.

Violating setup/hold can leave the internal node metastable — neither valid high nor low for an unbounded analog resolution time. A synchronizer cannot guarantee absence; it gives metastability time to decay and reduces probability exponentially. Multi-bit transfers need handshake, FIFO, Gray code, or another protocol that preserves word coherence; synchronizing each bit independently is not sufficient.

Registers and counters #

A register is a bank of storage elements with shared clock/control. Shift registers move data serially, parallel-load registers capture words, and enable logic either holds state or selects new data. Prefer clock enable to gating a clock with ordinary combinational logic; dedicated clock-gating cells are designed to avoid runt pulses.

An asynchronous ripple counter clocks each stage from the previous output. It divides frequency naturally but intermediate bits change at different times, so decoded states glitch and maximum speed is limited by accumulated delay. A synchronous counter clocks all bits together and computes toggle/next-state conditions combinationally.

For an $N$-bit binary counter, state wraps modulo $2^N$ and bit $k$ divides the clock by $2^{k+1}$ in steady operation. Modulo-$M$ counters need a defined sequence for all unused states so they recover from power-up or upset.

Reset and asynchronous controls #

Asynchronous assertion can place hardware in a safe state without a clock. Deassertion near an edge can violate recovery/removal timing and release different registers on different cycles. A common pattern is asynchronous assert, synchronous deassert per clock domain.

Verification #

Write the state table, define reset and every unused state, prove reachable transitions, close setup/hold timing, and test clock-domain crossings. At hardware level, verify power-up, reset sequencing, minimum pulse widths, clock stop/start, and the decoded outputs during transitions — especially for ripple structures and asynchronous pins.