Logic Families, Noise Margins & Digital Interfaces

A digital input does not receive an abstract bit; it receives a voltage waveform. A logic family guarantees ranges in which that waveform is interpreted as low or high, currents the output can source/sink, and delays under stated supply, temperature, and load. The undefined interval between $V_{IL(max)}$ and $V_{IH(min)}$ is not a third logic level.

Prove DC compatibility #

For a source driving a destination,

$$NM_H=V_{OH(min)}-V_{IH(min)},$$

$$NM_L=V_{IL(max)}-V_{OL(max)}.$$

Both must be positive at the actual output currents and worst-case conditions. Fan-out is limited independently in high and low states by output current versus aggregate input current; at modern CMOS inputs, capacitive load and edge rate often constrain fan-out before DC current does.

CMOS and legacy bipolar logic #

CMOS uses complementary transistor networks and ideally draws little static input current. Dynamic power is approximately

$$P_{dyn}\approx \alpha C_LV_{DD}^2f,$$

where $\alpha$ is switching activity. During an edge, both pull-up and pull-down can conduct; a slow input can increase current and dwell in the high-gain region. Schmitt-trigger inputs provide defined hysteresis for slow/noisy signals when the datasheet permits that use.

TTL and ECL use bipolar structures with different thresholds, current direction, speed, and power tradeoffs. Their historical values are not universal interface constants. Modern families with labels such as HC, HCT, LVC, AHC, or AUC have distinct supplies, thresholds, drive, partial-power-down behavior, and input-tolerance rules.

flowchart LR
  DC["DC: VOH/VOL vs VIH/VIL<br/>and source/sink current"] --> VALID["valid interface"]
  AC["AC: edge, delay, skew,<br/>capacitance, interconnect"] --> VALID
  POWER["power states: startup,<br/>unpowered pins, back-power"] --> VALID
  LIMIT["absolute max + injection<br/>ESD/clamp paths"] --> VALID

Timing and interconnect #

Propagation delay is measured between specified thresholds under specified load. Rise/fall times affect downstream timing and dynamic power. When interconnect flight time is a meaningful fraction of edge time, the trace is a transmission line; series/source termination, parallel termination, return-plane continuity, connector impedance, and stubs may dominate.

Simultaneous switching creates supply droop and ground bounce through package inductance. Local decoupling supplies edge current, but placement and return loop determine effectiveness.

Power sequencing #

If an input is driven while its supply is off, internal protection structures may inject current and partially power the device. Use a family with characterized $I_{off}$ or partial-power-down support, isolate the path, or sequence supplies. Also verify output state during brownout, enable transitions, and reset release. Digital correctness begins at the pins, before Boolean logic.