ADCs, DACs, Sample-and-Hold & Converter Errors

An ADC does not “measure voltage” in one step. Its input network must acquire and hold the signal, a reference defines the code scale, an architecture compares or integrates, digital logic emits a code, and errors from every stage combine. A DAC performs the inverse mapping but still needs a reference, switching network, output interface, and settling interval.

Static transfer and error language #

For an ideal unipolar $N$-bit converter over full-scale range $V_{FS}$,

$$LSB=\frac{V_{FS}}{2^N}.$$

Quantization error for an ideal rounded code lies within approximately $\pm0.5$ LSB. Offset shifts the transfer; gain error changes slope after offset removal; differential nonlinearity (DNL) measures code-width deviation; integral nonlinearity (INL) measures transfer deviation from a reference line. Missing codes and non-monotonic DAC steps are stronger failures than ordinary gain error.

The ideal sine-wave quantization SNR is approximately

$$SNR_{ideal}=6.02N+1.76\ \mathrm{dB},$$

but effective number of bits from measured SINAD includes noise and distortion, not just quantization.

Architecture map #

flowchart TB
  AIN["analog input"] --> AAF["anti-alias filter"]
  AAF --> ACQ["sample/hold + acquisition"]
  ACQ --> CORE["ADC core + reference"]
  CLK["clock + jitter"] --> CORE
  CORE --> CODE["digital code"]
  CODE --> DAC["DAC switching network + reference"]
  DAC --> SET["settling / reconstruction"]
  SET --> AOUT["analog output"]

Acquisition and drive #

Many SAR inputs switch an internal capacitor onto the source during acquisition. The source, driver output impedance, RC filter, switch resistance, and sampling capacitor must settle to the required fraction of an LSB before conversion. Average input current can look tiny while edge current is large. An op amp that is precise at DC may be unstable or too slow driving this kickback load.

The reference is another switched load. Reference noise, impedance, decoupling, and recovery directly modulate code. Grounding is about return-current geometry, not merely naming nets AGND and DGND.

Dynamic limits #

Clock aperture jitter sets an SNR ceiling for a sine input:

$$SNR_{jitter}=-20\log_{10}(2\pi f_{in}t_j).$$

DAC code transitions can switch several elements at slightly different times, producing glitch impulse. Settling time includes slew plus linear settling to the specified error band. Reconstruction filtering removes images and switching energy; it does not repair non-monotonicity or reference error.

Design and verification #

Start with signal bandwidth, amplitude, source impedance, required total error, latency, and environment. Allocate error among reference, front end, acquisition, converter, clock, layout, and calibration. Verify coherent FFT metrics for AC, histogram/noise-free codes for DC, INL/DNL, missing codes, channel crosstalk, temperature drift, power sequencing, and representative source/load networks.