Comparators, Schmitt Triggers & Multivibrators

A comparator decides whether one analog voltage is greater than another. Near equality, noise and slow slew can produce repeated transitions. Positive feedback creates two thresholds, so the current output state determines how far the input must move before the next transition.

Comparator contract #

Ideal output is the sign of $v_+-v_-$. A real comparator adds input offset, bias current, common-mode limits, overdrive-dependent propagation delay, output topology, recovery behavior, minimum pulse constraints, and sometimes internal hysteresis. Open-drain outputs require a pull-up; push-pull outputs must not be wire-ORed.

The input slew rate and noise set timing uncertainty approximately as

$$\sigma_t\approx\frac{\sigma_v}{|dv/dt|}.$$

A cleaner reference or faster crossing can improve timing more than a nominally faster comparator.

Hysteresis creates memory #

stateDiagram-v2
  LOW --> HIGH: Vin rises above VTH+
  HIGH --> LOW: Vin falls below VTH-
  LOW --> LOW: VTH- < Vin < VTH+
  HIGH --> HIGH: VTH- < Vin < VTH+

The hysteresis width $V_{TH+}-V_{TH-}$ must exceed expected noise and ripple while remaining smaller than the valid signal excursion. Calculate thresholds using actual output high/low levels, reference impedance, resistor tolerances, and input bias current — not ideal rails.

Three timing states #

• A bistable has two stable states and changes only when triggered.
• A monostable has one stable state; a trigger enters a temporary state until an RC trajectory crosses a threshold.
• An astable has no stable state; feedback alternately charges and discharges a capacitor between thresholds.

For a capacitor charging through $R$ toward $V_F$ from $V_0$, the time to threshold $V_T$ is

$$t=-RC\ln\left(\frac{V_T-V_F}{V_0-V_F}\right).$$

This equation, applied separately to each state, is the general multivibrator timing law. Memorized $0.69RC$ forms are special cases with particular threshold fractions.

Retriggering, startup, and races #

A monostable must specify whether triggers during its active interval are ignored or extend the interval. An astable must have a defined startup asymmetry; an exactly symmetric ideal simulation may remain stuck until numerical noise breaks symmetry. Reset, output power-up state, threshold rail behavior, and capacitor discharge paths belong in the design.

When to use dedicated timing logic #

Discrete comparator timing is transparent and flexible. For tight accuracy, very long delay, low power, or wide temperature, capacitor leakage, input current, threshold drift, and resistor tolerance may dominate. A crystal/clock plus counter or a timer IC with characterized thresholds can provide a better contract. Choose based on error budget, not schematic part count.